Line data Source code
1 : /*
2 : * Copyright (C) 2007-2014 Free Software Foundation, Inc.
3 : *
4 : * This file is free software; you can redistribute it and/or modify it
5 : * under the terms of the GNU General Public License as published by the
6 : * Free Software Foundation; either version 3, or (at your option) any
7 : * later version.
8 : *
9 : * This file is distributed in the hope that it will be useful, but
10 : * WITHOUT ANY WARRANTY; without even the implied warranty of
11 : * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 : * General Public License for more details.
13 : *
14 : * Under Section 7 of GPL version 3, you are granted additional
15 : * permissions described in the GCC Runtime Library Exception, version
16 : * 3.1, as published by the Free Software Foundation.
17 : *
18 : * You should have received a copy of the GNU General Public License and
19 : * a copy of the GCC Runtime Library Exception along with this program;
20 : * see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
21 : * <http://www.gnu.org/licenses/>.
22 : */
23 :
24 : /* %ecx */
25 : #define bit_SSE3 (1 << 0)
26 : #define bit_PCLMUL (1 << 1)
27 : #define bit_LZCNT (1 << 5)
28 : #define bit_SSSE3 (1 << 9)
29 : #define bit_FMA (1 << 12)
30 : #define bit_CMPXCHG16B (1 << 13)
31 : #define bit_SSE4_1 (1 << 19)
32 : #define bit_SSE4_2 (1 << 20)
33 : #define bit_MOVBE (1 << 22)
34 : #define bit_POPCNT (1 << 23)
35 : #define bit_AES (1 << 25)
36 : #define bit_XSAVE (1 << 26)
37 : #define bit_OSXSAVE (1 << 27)
38 : #define bit_AVX (1 << 28)
39 : #define bit_F16C (1 << 29)
40 : #define bit_RDRND (1 << 30)
41 :
42 : /* %edx */
43 : #define bit_CMPXCHG8B (1 << 8)
44 : #define bit_CMOV (1 << 15)
45 : #define bit_MMX (1 << 23)
46 : #define bit_FXSAVE (1 << 24)
47 : #define bit_SSE (1 << 25)
48 : #define bit_SSE2 (1 << 26)
49 :
50 : /* Extended Features */
51 : /* %ecx */
52 : #define bit_LAHF_LM (1 << 0)
53 : #define bit_ABM (1 << 5)
54 : #define bit_SSE4a (1 << 6)
55 : #define bit_PRFCHW (1 << 8)
56 : #define bit_XOP (1 << 11)
57 : #define bit_LWP (1 << 15)
58 : #define bit_FMA4 (1 << 16)
59 : #define bit_TBM (1 << 21)
60 :
61 : /* %edx */
62 : #define bit_MMXEXT (1 << 22)
63 : #define bit_LM (1 << 29)
64 : #define bit_3DNOWP (1 << 30)
65 : #define bit_3DNOW (1 << 31)
66 :
67 : /* Extended Features (%eax == 7) */
68 : /* %ebx */
69 : #define bit_FSGSBASE (1 << 0)
70 : #define bit_BMI (1 << 3)
71 : #define bit_HLE (1 << 4)
72 : #define bit_AVX2 (1 << 5)
73 : #define bit_BMI2 (1 << 8)
74 : #define bit_RTM (1 << 11)
75 : #define bit_AVX512F (1 << 16)
76 : #define bit_RDSEED (1 << 18)
77 : #define bit_ADX (1 << 19)
78 : #define bit_AVX512PF (1 << 26)
79 : #define bit_AVX512ER (1 << 27)
80 : #define bit_AVX512CD (1 << 28)
81 : #define bit_SHA (1 << 29)
82 :
83 : /* %ecx */
84 : #define bit_PREFETCHWT1 (1 << 0)
85 :
86 : /* Extended State Enumeration Sub-leaf (%eax == 13, %ecx == 1) */
87 : #define bit_XSAVEOPT (1 << 0)
88 :
89 : /* Signatures for different CPU implementations as returned in uses
90 : of cpuid with level 0. */
91 : #define signature_AMD_ebx 0x68747541
92 : #define signature_AMD_ecx 0x444d4163
93 : #define signature_AMD_edx 0x69746e65
94 :
95 : #define signature_CENTAUR_ebx 0x746e6543
96 : #define signature_CENTAUR_ecx 0x736c7561
97 : #define signature_CENTAUR_edx 0x48727561
98 :
99 : #define signature_CYRIX_ebx 0x69727943
100 : #define signature_CYRIX_ecx 0x64616574
101 : #define signature_CYRIX_edx 0x736e4978
102 :
103 : #define signature_INTEL_ebx 0x756e6547
104 : #define signature_INTEL_ecx 0x6c65746e
105 : #define signature_INTEL_edx 0x49656e69
106 :
107 : #define signature_TM1_ebx 0x6e617254
108 : #define signature_TM1_ecx 0x55504361
109 : #define signature_TM1_edx 0x74656d73
110 :
111 : #define signature_TM2_ebx 0x756e6547
112 : #define signature_TM2_ecx 0x3638784d
113 : #define signature_TM2_edx 0x54656e69
114 :
115 : #define signature_NSC_ebx 0x646f6547
116 : #define signature_NSC_ecx 0x43534e20
117 : #define signature_NSC_edx 0x79622065
118 :
119 : #define signature_NEXGEN_ebx 0x4778654e
120 : #define signature_NEXGEN_ecx 0x6e657669
121 : #define signature_NEXGEN_edx 0x72446e65
122 :
123 : #define signature_RISE_ebx 0x65736952
124 : #define signature_RISE_ecx 0x65736952
125 : #define signature_RISE_edx 0x65736952
126 :
127 : #define signature_SIS_ebx 0x20536953
128 : #define signature_SIS_ecx 0x20536953
129 : #define signature_SIS_edx 0x20536953
130 :
131 : #define signature_UMC_ebx 0x20434d55
132 : #define signature_UMC_ecx 0x20434d55
133 : #define signature_UMC_edx 0x20434d55
134 :
135 : #define signature_VIA_ebx 0x20414956
136 : #define signature_VIA_ecx 0x20414956
137 : #define signature_VIA_edx 0x20414956
138 :
139 : #define signature_VORTEX_ebx 0x74726f56
140 : #define signature_VORTEX_ecx 0x436f5320
141 : #define signature_VORTEX_edx 0x36387865
142 :
143 : #if defined(__i386__) && defined(__PIC__)
144 : /* %ebx may be the PIC register. */
145 : #if __GNUC__ >= 3
146 : #define __cpuid(level, a, b, c, d) \
147 : __asm__ ("xchg{l}\t{%%}ebx, %k1\n\t" \
148 : "cpuid\n\t" \
149 : "xchg{l}\t{%%}ebx, %k1\n\t" \
150 : : "=a" (a), "=&r" (b), "=c" (c), "=d" (d) \
151 : : "0" (level))
152 :
153 : #define __cpuid_count(level, count, a, b, c, d) \
154 : __asm__ ("xchg{l}\t{%%}ebx, %k1\n\t" \
155 : "cpuid\n\t" \
156 : "xchg{l}\t{%%}ebx, %k1\n\t" \
157 : : "=a" (a), "=&r" (b), "=c" (c), "=d" (d) \
158 : : "0" (level), "2" (count))
159 : #else
160 : /* Host GCCs older than 3.0 weren't supporting Intel asm syntax
161 : nor alternatives in i386 code. */
162 : #define __cpuid(level, a, b, c, d) \
163 : __asm__ ("xchgl\t%%ebx, %k1\n\t" \
164 : "cpuid\n\t" \
165 : "xchgl\t%%ebx, %k1\n\t" \
166 : : "=a" (a), "=&r" (b), "=c" (c), "=d" (d) \
167 : : "0" (level))
168 :
169 : #define __cpuid_count(level, count, a, b, c, d) \
170 : __asm__ ("xchgl\t%%ebx, %k1\n\t" \
171 : "cpuid\n\t" \
172 : "xchgl\t%%ebx, %k1\n\t" \
173 : : "=a" (a), "=&r" (b), "=c" (c), "=d" (d) \
174 : : "0" (level), "2" (count))
175 : #endif
176 : #elif defined(__x86_64__) && (defined(__code_model_medium__) || defined(__code_model_large__)) && defined(__PIC__)
177 : /* %rbx may be the PIC register. */
178 : #define __cpuid(level, a, b, c, d) \
179 : __asm__ ("xchg{q}\t{%%}rbx, %q1\n\t" \
180 : "cpuid\n\t" \
181 : "xchg{q}\t{%%}rbx, %q1\n\t" \
182 : : "=a" (a), "=&r" (b), "=c" (c), "=d" (d) \
183 : : "0" (level))
184 :
185 : #define __cpuid_count(level, count, a, b, c, d) \
186 : __asm__ ("xchg{q}\t{%%}rbx, %q1\n\t" \
187 : "cpuid\n\t" \
188 : "xchg{q}\t{%%}rbx, %q1\n\t" \
189 : : "=a" (a), "=&r" (b), "=c" (c), "=d" (d) \
190 : : "0" (level), "2" (count))
191 : #else
192 : #define __cpuid(level, a, b, c, d) \
193 : __asm__ ("cpuid\n\t" \
194 : : "=a" (a), "=b" (b), "=c" (c), "=d" (d) \
195 : : "0" (level))
196 :
197 : #define __cpuid_count(level, count, a, b, c, d) \
198 : __asm__ ("cpuid\n\t" \
199 : : "=a" (a), "=b" (b), "=c" (c), "=d" (d) \
200 : : "0" (level), "2" (count))
201 : #endif
202 :
203 : /* Return highest supported input value for cpuid instruction. ext can
204 : be either 0x0 or 0x8000000 to return highest supported value for
205 : basic or extended cpuid information. Function returns 0 if cpuid
206 : is not supported or whatever cpuid returns in eax register. If sig
207 : pointer is non-null, then first four bytes of the signature
208 : (as found in ebx register) are returned in location pointed by sig. */
209 :
210 : static __inline unsigned int
211 3 : __get_cpuid_max (unsigned int __ext, unsigned int *__sig)
212 : {
213 : unsigned int __eax, __ebx, __ecx, __edx;
214 :
215 : #ifndef __x86_64__
216 : /* See if we can use cpuid. On AMD64 we always can. */
217 : #if __GNUC__ >= 3
218 3 : __asm__ ("pushf{l|d}\n\t"
219 : "pushf{l|d}\n\t"
220 : "pop{l}\t%0\n\t"
221 : "mov{l}\t{%0, %1|%1, %0}\n\t"
222 : "xor{l}\t{%2, %0|%0, %2}\n\t"
223 : "push{l}\t%0\n\t"
224 : "popf{l|d}\n\t"
225 : "pushf{l|d}\n\t"
226 : "pop{l}\t%0\n\t"
227 : "popf{l|d}\n\t"
228 : : "=&r" (__eax), "=&r" (__ebx)
229 : : "i" (0x00200000));
230 : #else
231 : /* Host GCCs older than 3.0 weren't supporting Intel asm syntax
232 : nor alternatives in i386 code. */
233 : __asm__ ("pushfl\n\t"
234 : "pushfl\n\t"
235 : "popl\t%0\n\t"
236 : "movl\t%0, %1\n\t"
237 : "xorl\t%2, %0\n\t"
238 : "pushl\t%0\n\t"
239 : "popfl\n\t"
240 : "pushfl\n\t"
241 : "popl\t%0\n\t"
242 : "popfl\n\t"
243 : : "=&r" (__eax), "=&r" (__ebx)
244 : : "i" (0x00200000));
245 : #endif
246 :
247 3 : if (!((__eax ^ __ebx) & 0x00200000))
248 0 : return 0;
249 : #endif
250 :
251 : /* Host supports cpuid. Return highest supported cpuid input value. */
252 3 : __cpuid (__ext, __eax, __ebx, __ecx, __edx);
253 :
254 3 : if (__sig)
255 0 : *__sig = __ebx;
256 :
257 3 : return __eax;
258 : }
259 :
260 : /* Return cpuid data for requested cpuid level, as found in returned
261 : eax, ebx, ecx and edx registers. The function checks if cpuid is
262 : supported and returns 1 for valid cpuid information or 0 for
263 : unsupported cpuid level. All pointers are required to be non-null. */
264 :
265 : static __inline int
266 3 : __get_cpuid (unsigned int __level,
267 : unsigned int *__eax, unsigned int *__ebx,
268 : unsigned int *__ecx, unsigned int *__edx)
269 : {
270 3 : unsigned int __ext = __level & 0x80000000;
271 :
272 3 : if (__get_cpuid_max (__ext, 0) < __level)
273 0 : return 0;
274 :
275 3 : __cpuid (__level, *__eax, *__ebx, *__ecx, *__edx);
276 3 : return 1;
277 : }
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